1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices. More specifically, the present invention relates to a method of fabricating semiconductor devices, wherein a lower layer is prevented from being attacked due to deformation and loss of an etch mask when forming a trench for isolation in a cell region.
2. Discussion of Related Art
Generally, a semiconductor device includes an isolation region for electrically separating individual circuit patterns. More particularly, as semiconductor devices are high integrated and miniaturized, development into the shrinkage of an isolation region as well as the shrinkage of the size of an individual element is actively in progress. This is because formation of the isolation region greatly influences the size of an active region and process margin of subsequent process steps, as an initial manufacturing step of all semiconductor devices.
Recently, a LOCOS isolation method that has been widely used in fabrication of semiconductor devices forms an isolation region having a relatively wide area, and reaches a limit as semiconductor devices are highly integrated. Accordingly, a trench isolation method in which some of a substrate is etched to form trenches, thereby isolating elements has been proposed as technology suitable for isolation of high-integrated semiconductor devices.
Meanwhile, among semiconductor devices, flash memory devices in which stored information is not erased although external power is off have been spotlighted and widely used in memory cards. The flash memory devices need a high voltage in program and erase operations. Accordingly, a semiconductor substrate of a flash memory device has characteristics in that it has to include a peripheral region in which a high voltage circuit will be formed as well as a cell region in which data will be stored, wherein the peripheral region has to be wider than the cell region, and an isolation film of the peripheral region has to be greater than a width and depth of the isolation film of the cell region. In order to fulfill the characteristics of this flash memory device, a dual trench isolation structure in which an isolation film of the peripheral region is deeper than an isolation film of the cell region has been proposed.
As such, in order to form isolation films having different depths in the cell region and the peripheral region, respectively, a photomask process and an etch process have to be performed on each of the cell region and the peripheral region. The peripheral region has to use a photoresist for KrF since it has a great pattern size. The cell region has to use a photoresist for ArF, which can be patterned finely, since it has a small pattern size.
The photoresist for KrF, which uses KrF light (248 nm) as an exposure light, does not become problematic upon etching of trenches because it is not weak in plasma and can be formed thickly. However, the photoresist for ArF, which uses ArF light (193 nm) as exposure light, can be lost upon etching of trenches because it is thin in thickness and weak in plasma. Further, the photoresist for ArF can be deformed due to plasma used in a trench etching process, and thus attacks a lower layer and a semiconductor substrate.
More particularly, in nano technologies, as overlay margin between a floating gate and an isolation film decreases, a pad nitride film, which serves as an anti-polish film in a subsequent CMP process of a polysilicon film, is lost in the case of introducing a self-aligned floating gate (SAFG) scheme. Accordingly, a thickness of the pad nitride film is increased about 1000 to 2000 Å. This makes it impossible to etch trenches using a photoresist for ArF.